1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device which is usable as both a static type memory and a read-only memory and a method of operating the same.
2. Description of the Background Art
FIG. 16 is a block diagram showing a structure of a conventional and general static random access memory (hereinafter referred to as SRAM).
In a memory cell array la, a plurality of word lines WL and a plurality of bit line pairs BL, BL are arranged so as to cross each other, and memory cells 2a are provided on their crossings. Then, a power supply potential (hereinafter referred to a supply potential) Vcc is supplied by a supply line 3, and the ground potential GND (0 V) is supplied by a ground line 4 to memory cell array 1a.
A row decoder 5, a column decoder 6, and an input/output circuit 8 are provided in relation to memory cell array 1a. Row decoder 5 decodes the row address signal of the address signal AD supplied through an address input line 7, selects one of the plurality of word lines WL, and provides a voltage of a high level or "H" corresponding to the supply potential Vcc to the selected word line WL. Input/output circuit 8 includes a plurality of switching circuits provided on each of bit line pairs BL, BL and one sense amplifier or a plurality of sense amplifiers provided between a data input/output line 9 and each switching circuit. Column decoder 6 decodes the column address signal of the address signal AD supplied through address input line 7, selects one of the plurality of switching circuits in input/output circuit 8, and renders the selected switching circuit in conducting state.
Thus, one of the plurality of memory cells 2a is selected by row decoder 5 and column decoder 6. When data is written, the externally provided data D is written in the selected memory cell 2a selected through data input/output line 9 and input/output circuit 8. When data is read, the data stored in the selected memory cell 2a is read to the outside through data input/output circuit 8 and data input/output line 9.
FIG. 17 is a circuit diagram showing the structure of the memory cell 2a shown in FIG. 16.
Memory cell 2a includes P channel MOS transistors 21, 22 and N channel MOS transistors 23, 24, 25, and 26. Transistor 21 is connected between a node N1 and a node NA and transistor 23 is connected between node NA and a node N3. Transistor 22 is connected between node N2 and a node NB, and transistor 24 is connected between node NB and N4. The gates of the transistors 21, 23 are connected to node NB, and the gates of transistors 22, 24 are connected to node NA. Nodes N1, N2 are connected to supply line 3 and nodes N3, N4 are connected to ground line 4. Transistors 21, 23 constitute a first inverter, and transistors 22, 24 constitute a second inverter. Potential which are complementary to each other are provided to node NA and NB.
Transistor 25 is connected between bit line BL and node NA, and transistor 26 is connected between bit line BL and node NB. The gates of transistors 25, 26 are connected to word line WL. The memory cell 2a shown in FIG. 17 is refereed to as a CMOS type memory cell.
Now, the write operation of the memory cell 2a shown in FIG. 17 will be described.
The data externally provided is supplied through data input/output line 9 and input/output circuit 8 to bit line pair BL, BL. When the data "1" is written, the potential at bit line BL becomes "H", and the potential at bit line BL becomes a low level or "L". When a word line WL is selected by row decoder 5, the potential at this word line WL rises to "H". As a result, transistors 25, 26 turn on. Consequently, the potential at node NA becomes "H", and the potential at node NB becomes "L". As a result, transistor 24 turns on, and transistor 22 turns off. Then, transistor 21 turns on, and transistor 23 turns off. Therefore, the potential at node NA is pulled up through transistor 21 to the supply potential, and the potential at node NB is pulled down through transistor 24 to the ground potential. Thus, the data "1" is stored in memory cell 2a.
When the data "0" is written, an operation opposite to the above described operation is performed.
Now, the write operation of the memory cell 2a shown in FIG. 17 will be described.
First, when a word line WL is selected by row decoder 5, the potential at the word line WL rises to "H". As a result, transistors 25, 26 turn on, and the potentials held at node NA and NB are transferred to bit line BL and BL, respectively. In the case where the data "1" is stored in memory cell 2a, the potential at bit line BL becomes "H", and the potential at bit line BL becomes "L". Conversely, in the case where data "0" is stored in memory cell 2a, the potential at bit line BL becomes "L", and the potential at bit line BL becomes "H".
Thus, the data read out to bit line pair BL, BL is supplied to the outside as an output through input/output circuit 8 and data input/output line 9.
Thus, memory cell 2a in FIG. 17 operates as a static type memory cell. Therefore, even if each memory cell is not periodically refreshed in the SRAM in FIG. 16 as in Dynamic Random Access Memory (DRAM), each memory cell 2a can statically store data as long as the supply potential Vcc is provided to supply line 3.
In the conventional SRAM described above, however, if the supply potential Vcc is stopped from being supplied to supply line 3, the data stored in each memory cell 2a is lost. More specifically, in a conventional SRAM, it is impossible to fixedly store data as in a read-only memory (hereinafter referred to as ROM). In accordance with diversification of systems in recent years, semiconductor memory devices of multifunction came to be demanded, and implementation of semiconductor memory devices having both the functions of SRAM and ROM is strongly demanded.
Therefore, a semiconductor memory device having both the functions of SRAM and ROM has been developed by the inventors of the present application.
FIG. 18 is a block diagram which shows a structure of a conventional semiconductor memory device having both the functions of SRAM and ROM. This semiconductor memory device is disclosed in Patent Laying Open No. Hei 1-130395 and the corresponding U.S. Ser. No. 526,138.
A plurality of word lines WL and a plurality of bit line pairs, Bl, BL are arranged in a memory cell array 1b so as to cross each other, and memory cells 2b are provided at the crossings of them. A first potential Vcc1 is supplied through a first supply line 31, a second potential Vcc2 is supplied through a second supply line 32, and a ground potential GND is supplied through ground line 4 to memory cell array 1b. The other parts of the structure are the same as the structure of the semiconductor memory device in FIG. 16.
FIG. 19 is a circuit diagram which shows the structure of memory cell 2b shown in FIG. 18.
In Memory cell 2b, high resistance load devices 21a, 22a are provided instead of transistors 21, 22 in memory cell 2a in FIG. 17. High resistance load device 21a is connected between node N1 and node NA, and high resistance load device 22a is connected between node N2 and node NB. Node N1 is connected to first supply line 31, and node N2 is connected to second supply line 32. This memory cell 2b is referred to as a high resistance load type memory cell.
Now, the operation of the memory cell 2b shown in FIG. 19 will be described.
First, if potentials Vcc1 and Vcc2 are set to the supply potential Vcc, memory cell 2b operates as an ordinary static type memory cell like the memory cell 2a in FIG. 17.
Then, if potential Vcc1 is set to the supply potential Vcc and potential Vcc2 is set to the ground potential, the potentials at nodes N2, NB become "L". Therefore, transistor 23 turns off. Accordingly, the potential at node NA is pulled up to the supply potential Vcc. As a result, transistor 24 turns on. Therefore, the potential at node NB is pulled down to the ground potential. Specifically, this memory cell 2b comes to fixedly store the data "1". In this case, memory cell 2b operates as a ROM cell storing the data "1".
Conversely, if potential Vcc1 is set to the ground potential and potential Vcc2 is set to the supply potential Vcc, memory cell 2b makes an operation opposite to the above described operation. Specifically, this memory cell 2b fixedly stores the data "0". In this case, memory cell 2b operates as a ROM cell storing the data "0".
If potentials Vcc1 and Vcc2 are set to the ground potential GND, both the potentials at nodes NA, NB become "L". Therefore, it is impossible to specify the data to be stored in memory cell 2b.
As described above, according to the semiconductor memory device shown in FIGS. 18 and 19, the semiconductor memory device can be used as any of SRAM and ROM, as per the potentials provided to first and second supply lines 31, 32.
However, either of the two supply lines 31, 32 is normally used to provide the supply potential Vcc to the whole of the semiconductor memory device. In the case where first supply line 31 is used for providing the supply potential Vcc to the whole of the semiconductor memory device, a user can use the semiconductor memory device as SRAM or ROM by setting potential Vcc2, which is fed to second supply line 32, to provide potential Vcc or ground potential GND.
In this case, if potential Vcc2 is set to the supply potential Vcc, memory cell 2b operates as a static type memory cell. Moreover, if potential Vcc2 is set to the ground potential GND, memory cell 2b operates as ROM cell storing the data "1". In this case, however, memory cell 2b cannot be used as a ROM cell storing the data "0".
Thus, it is difficult for a user to use memory cell 2b as a ROM storing any data.